| 摘要 |
Included is a first transistor for controlling rewriting and reading of a first data, a second transistor for controlling rewriting and reading of a second data, a first inverter including an input terminal for the first data, a second inverter including an input terminal for the second data, a third transistor between an output terminal of the second inverter and the input terminal of the first inverter, a fourth transistors between the output of the first inverter and the input terminal of the second inverter, a fifth transistor for controlling rewriting and reading of the first data in the first capacitor, and a sixth transistor for controlling rewriting and reading of the second data in a second capacitor. The first data and the second data are held in the first capacitor and the second capacitor even while power supply is cut off.
|
