| 摘要 |
PROBLEM TO BE SOLVED: To more improve ESD resistance of a circuit side which receives a signal. SOLUTION: An inverter circuit INV1 is connected to a ground wiring GND1 for power supply, and connected to a power supply wiring VDD1 through a PMOS transistor MP5. An inverter circuit INV2 is connected to a ground wiring GND2 and a power supply wiring VDD2 for power supply, and an input node is connected to an output node of the inverter circuit INV1. Further, the ground wiring GND1 and ground wiring GND2 are connected to each other through a protective element PE0. In normal operation, an output of the inverter circuit INV3 rises to H level, an output of the inverter circuit INV4 falls to L level, and the PMOS transistor MP5 turns on. During ESD application, the power supply wiring VDD2 enters a floating state, the output of the inverter circuit INV4 rises to H level, and the PMOS transistor MP5 turns off, so that a current accompanying the ESD application does not flow in the inverter circuit INV2. COPYRIGHT: (C)2011,JPO&INPIT |
