| 摘要 |
A semiconductor memory device includes a first active region, a second active region, an element isolation region, memory cell transistors. Each of memory cell transistors includes a laminated gate and a first impurity diffusion layer functioning as a source and a drain. The laminated gate includes a first insulating film, a second insulating film, and a control gate electrode. The second insulating film is commonly connected between the plurality of memory cell transistors to step over the element isolation region and is in contact with an upper surface of the element isolation region. An upper surface of the element isolation region is higher than a bottom surface of the first insulating film and is located under the upper surface of the first insulating film. |
