RAM single event upset (SEU) method to correct errors

摘要

An error detection and correction (EDAC) circuit (20) mitigates the effect of single event upsets (SEU) events in a redundant memory system (10). The EDAC circuit (20) includes a first input for receiving first data and parity information stored by a first memory device (16) and a second input for receiving second data and parity information stored by a second memory device (18). First parity check logic (50a) calculates parity for the received first data and parity information. Second parity check logic (50b) calculates parity for the received second data and parity information. Bit comparison logic detects (52) differences between the first data and the second data, and between the first parity information and the second parity information. Based on the parity check calculated for the first and second data, and the bit comparison, data select logic (54) selects either the first data or the second data for provision to a data bus (38).