发明名称 Method for predicting tolerable spacing between conductors in semiconductor process
摘要 A method for predicting tolerable contact-to-gate spacing is provided. At first, a wafer with a plurality of source/drain contacts are provided. Then, a plurality of testing gate lines are formed on the wafer by using a photomask. In one die, there are different contact-to-gate distances ranging from d+Deltad to d-Deltad wherein d is the standard spacing and Deltad<d. Then, the wafer is inspected to find failure counts corresponding to each contact-to-gate distance. The tolerable spacing is determined according to the failure counts and the contact-to-gate distances based on a statistical method.
申请公布号 US8516400(B2) 申请公布日期 2013.08.20
申请号 US20100941652 申请日期 2010.11.08
申请人 KUO CHIEN-LI;LIAO WEN-JUNG;LIAO JIUN-HAU;HSIEH MIN-CHIN;HOU CHUN-LIANG;LEI SHUEN-CHENG;UNITED MICROELECTRONICS CORP. 发明人 KUO CHIEN-LI;LIAO WEN-JUNG;LIAO JIUN-HAU;HSIEH MIN-CHIN;HOU CHUN-LIANG;LEI SHUEN-CHENG
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项
地址
您可能感兴趣的专利