| 摘要 |
A clock signal generation circuit includes a clock delay control signal generation unit configured to divide a clock signal to generate a divided clock signal, generate a plurality of periodic signals which have different periods with each other during a half period of the divided clock signal, and output clock delay control signals from the plurality of periodic signals, and a doubler clock generation unit configured to delay the clock signal in response to the clock delay control signals to generate a delayed clock signal, and generate an output clock signal by mixing phases of the clock signal and the delayed clock signal.
|
