发明名称 |
Error correcting code protected quasi-static bit communication on a high-speed bus |
摘要 |
A communication interface device, system, method, and design structure for error correcting code (ECC) protected quasi-static bit communication (SBC) on a high-speed bus are provided. The communication interface device includes high-speed sampling logic to capture high-speed data from the high-speed bus using a high-speed sampling clock and SBC sampling logic to capture SBC samples from the high-speed bus using an SBC sampling clock. The SBC sampling clock is slower than the high-speed sampling clock. The communication interface device also includes an SBC finite state machine (FSM) to detect a received SBC command in response to a static pattern persisting for a predetermined number of the SBC samples and command decoding logic to decode the received SBC command.
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申请公布号 |
US8516338(B2) |
申请公布日期 |
2013.08.20 |
申请号 |
US201213535574 |
申请日期 |
2012.06.28 |
申请人 |
BUCHMANN PETER;GOWER KEVIN C.;REESE ROBERT J.;SCHMATZ MARTIN L.;TROMBLEY MICHAEL R.;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BUCHMANN PETER;GOWER KEVIN C.;REESE ROBERT J.;SCHMATZ MARTIN L.;TROMBLEY MICHAEL R. |
分类号 |
H03M13/00 |
主分类号 |
H03M13/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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