发明名称 |
Technique for verifying the microstructure of lead-free interconnects in semiconductor assemblies |
摘要 |
A method for verifying the internal microstructure of interconnects in flip-chip applications includes providing a microelectronic assembly comprising the following: a substrate hosting an array of flip-chip attach pads and one or more process control pads; a flip chip having an array of solder bumps in contact with the array of flip-chip attach pads; and one or more representative solder bumps contacting the one or more process control pads. The representative solder bumps have a substantially similar or identical chemical composition as the array of solder bumps. A reflow cycle is then applied to the microelectronic assembly to melt and solidify the array of solder bumps on the flip-chip attach pads and melt and solidify the representative solder bumps on the process control pads. The surface texture of the representative solder bumps is then optically inspected to determine an internal microstructure of the array of solder bumps.
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申请公布号 |
US8514386(B2) |
申请公布日期 |
2013.08.20 |
申请号 |
US201113115823 |
申请日期 |
2011.05.25 |
申请人 |
BERGERON CHRISTIAN;BLAIS PASCAL;FORTIN CLEMENT;GUERIN LUC;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BERGERON CHRISTIAN;BLAIS PASCAL;FORTIN CLEMENT;GUERIN LUC |
分类号 |
G01N21/00;G01N21/88 |
主分类号 |
G01N21/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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