| 摘要 |
<p>PURPOSE: A semiconductor memory device and a semiconductor integrated circuit including the same are provided to improve the reliability of the semiconductor memory device by controlling to make a data signal be correctly inputted by multiple control signals having a constant margin. CONSTITUTION: A memory cell region (210) has 8 bank structures and a SerDes data I/O structure for reducing the number of data I/O lines. One bank is made of 8 octet banks. A control unit (250) generates a control signal to make data be correctly inputted to all banks even in the SerDes structure which is the same as the memory cell region by synchronizing a command signal and an address signal with the same clock. [Reference numerals] (100) Memory control device; (210) Memory cell region; (220) Data receiving unit; (230) Command receiving unit; (240) Address receiving unit; (250) Control unit; (260) Data latch aligning unit</p> |
