发明名称 Low Voltage CMOS Power on Reset Circuit
摘要 An electronic circuit includes an illustrative low voltage CMOS power on reset circuit. The electronic circuit can comprise a power on reset circuit coupled between a supply voltage terminal and a signal node. The illustrative power on reset circuit comprises a voltage detector coupled to the supply voltage terminal which is configured to track CMOS thresholds and deactivate when supply voltage reaches a level for proper operation of CMOS logic.
申请公布号 US2013207696(A1) 申请公布日期 2013.08.15
申请号 US201213371307 申请日期 2012.02.10
申请人 GONZALEZ DAVID M. 发明人 GONZALEZ DAVID M.
分类号 H03L7/00 主分类号 H03L7/00
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