| 摘要 |
<p>The present invention has the objective of resolving bottlenecks in loop processing so as to perform parallel processing at high speed, wherein a plurality of processing units each have: an input/output unit which acquires only packets for which destination information calculated on the basis of at least a portion of extended identification information indicates the processing unit; a calculating unit which executes a processing instruction to be initially executed among processing instructions of the packets acquired by the input/output unit so as to generate packets for which extended identification information, which treats a processing instruction to be executed next after the executed processing instruction as the processing instruction to be initially executed, has been added to data generated by the first-mentioned execution in order to input the same into the input/output unit; a template storage unit which, if the processing instruction to be initially executed is a processing instruction that generates a packet group comprising a plurality of packets, registers template information for generating the packet group; and a packet generation unit which generates the packet group on the basis of the template information registered in the template storage unit in order to input the same into the input/output unit.</p> |
