发明名称 |
CACHE PREFETCH DURING A HIERARCHICAL MOTION ESTIMATION |
摘要 |
An apparatus having a cache and a processor is disclosed. The cache may be configured to (i) buffer a first subset of a reference picture to facilitate a motion estimation of a current block at a first level of a hierarchical motion estimation and (ii) prefetch a second subset of the reference picture to the cache in response to an occurrence of a condition before the motion estimation is completed at the first level. The processor may be configured to calculate a plurality of scores by comparing the current block with the first subset of the reference picture. The second subset generally (i) resides at a second level of the hierarchical motion estimation and (ii) may be determined from the scores calculated prior to the occurrence of the condition.
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申请公布号 |
US2013208796(A1) |
申请公布日期 |
2013.08.15 |
申请号 |
US201213396904 |
申请日期 |
2012.02.15 |
申请人 |
AMITAY AMICHAY;RABINOVITCH ALEXANDER;DUBROVIN LEONID |
发明人 |
AMITAY AMICHAY;RABINOVITCH ALEXANDER;DUBROVIN LEONID |
分类号 |
H04N7/32;H04N7/26 |
主分类号 |
H04N7/32 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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