STUB MINIMIZATION FOR WIREBOND STACKED ASSEMBLIES WITHOUT WINDOWS

摘要

A microelectronic package (100) can include a plurality of vertically stacked semiconductor chips 632, 637, the front face of at least one chip facing away from a first substrate surface (108), one or more columns (138, 143) of contacts (132) extending in a first direction (142) along surface (108). Columns (104A, 107B, 109A, 109B) of terminals (105 107) exposed at a second substrate surface (110) extend in the first direction. First terminals (105) disposed in a central region (112) of surface (110) which has width (152) not more than three and one-half times a minimum pitch (150) of the columns of terminals can be configured to carry address information usable to determine an addressable memory location. An axial plane of the at least one semiconductor chip can intersect the central region.