发明名称 |
INTEGRATED CIRCUIT DEVICE AND TEST METHOD |
摘要 |
PROBLEM TO BE SOLVED: To provide an integrated circuit device for suppressing skew and jitter of a clock signal.SOLUTION: An integrated circuit device 400A includes a chip 100A and a package substrate 410A. The chip 100A includes a clock driver 150 for outputting a clock signal and a clock receiver 160 for receiving the clock signal. The package substrate 410A includes: a clock signal line 420 which transmits the clock signal outputted from the clock driver 150; and a power source line 430 and a ground line 440 which directly supply electric power to the clock driver 150 and the clock receiver 160. |
申请公布号 |
JP2013157436(A) |
申请公布日期 |
2013.08.15 |
申请号 |
JP20120016470 |
申请日期 |
2012.01.30 |
申请人 |
FUJITSU SEMICONDUCTOR LTD |
发明人 |
ANDOU NARIYOSHI |
分类号 |
H05K1/02;H01L21/822;H01L27/04 |
主分类号 |
H05K1/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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