| 摘要 |
PROBLEM TO BE SOLVED: To perform a delay failure analysis between clock domains constituting a function block by solving a problem in which a timing adjustment between a clock edge in a clock domain on a data transmission side and a clock edge in a clock domain on a data reception side becomes difficult to perform if the circuit scale of the function block increases.SOLUTION: A clock generation circuit (TCTL) supplies an AC scan test clock (CLK) that has two clock pulses to respective clock domains (CD_N, N=0 to n-1) that constitute a function block (IP). A clock control circuit (LCSC) included in each of the clock domains controls whether to generate a release clock and a capture clock in a domain test clock (GCLK) on the basis of a release clock control signal S0_CD_N and a capture clock control signal S1_CD_N, which are set in a test control register (TDR), and their two clock pulses. |
