| 摘要 |
A microprocessor capable of running both x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs, the microprocessor comprising:a mode indicator, that indicates whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program; and a plurality of hardware registers, wherein when the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions, the plurality of hardware registers store x86 ISA architectural state, wherein when the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions, the plurality of hardware registers store ARM ISA architectural state; wherein when one of the x86 ISA machine language program instructions writes a value to one of the plurality of hardware registers and one of the instructions of the ARM ISA machine language program subsequently reads the one of the plurality of hardware registers, the ARM ISA instruction receives the same value written by the x86 ISA instruction. |
