发明名称 Chip package including multiple sections for reducing chip package interaction
摘要 Thermally induced stress in a semiconductor die, i.e., in a complex metallization system thereof, may be reduced by "dividing" a package substrate into two or more substrate sections, which may have formed therebetween an appropriate stress buffer region, for instance a region of superior resiliency. In this case, the total deformation of the package substrate may be reduced, thereby also reducing the thermally induced stress forces in the complex metallization system of the semiconductor die. Hence, for a given size and complexity of a metallization system, an increased production yield and superior reliability may be achieved.
申请公布号 US8508053(B2) 申请公布日期 2013.08.13
申请号 US20100964359 申请日期 2010.12.09
申请人 CHUMAKOV DMYTRO;GLOBALFOUNDRIES INC. 发明人 CHUMAKOV DMYTRO
分类号 H01L29/40 主分类号 H01L29/40
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