发明名称 Semiconductor device
摘要 A write disturbance margin of reference cells that generate reference current during read is improved. A bit line forms a clad interconnect structure in the normal cell region where normal cells are disposed, and a partially clad or non-clad interconnect structure in the reference cell region where a reference cell is disposed. Thus, a writing magnetic field intensity applied to the reference cell is smaller than the write magnetic field intensity applied to a normal memory cell during identical write currents.
申请公布号 US8508987(B2) 申请公布日期 2013.08.13
申请号 US200913319461 申请日期 2009.05.27
申请人 TSUJI TAKAHARU;WATANABE GENTA;RENESAS ELECTRONICS CORPORATION 发明人 TSUJI TAKAHARU;WATANABE GENTA
分类号 G11C11/00 主分类号 G11C11/00
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