发明名称 Architecture and system for coordinated network-wide redundancy elimination
摘要 A network employing redundancy-aware hardware may actively allocate decompression tasks among different devices along a single path to improve data throughput. The allocation can be performed by a hash or similar process operating on a header of the packets to distribute caching according to predefined ranges of hash values without significant additional communication overhead. Decompression of packets may be similarly distributed by marking shim values to match the earlier caching of antecedent packets. Nodes may use coordinated cache sizes and organizations to eliminate the need for separate cache protocol communications.
申请公布号 US8509237(B2) 申请公布日期 2013.08.13
申请号 US20090492749 申请日期 2009.06.26
申请人 AKELLA SRINIVASA ADITYA;ANAND ASHOK;SEKAR VYAS;WISCONSIN ALUMNI RESEARCH FOUNDATION 发明人 AKELLA SRINIVASA ADITYA;ANAND ASHOK;SEKAR VYAS
分类号 H04L12/28 主分类号 H04L12/28
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