发明名称 Memory array circuit incorporating multiple array block selection and related method
摘要 Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
申请公布号 US8509025(B2) 申请公布日期 2013.08.13
申请号 US201113215134 申请日期 2011.08.22
申请人 SCHEUERLEIN ROY E.;FASOLI LUCA G.;SANDISK 3D LLC 发明人 SCHEUERLEIN ROY E.;FASOLI LUCA G.
分类号 G11C8/00 主分类号 G11C8/00
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