发明名称 Over stress verify design rule check
摘要 Some aspects of this disclosure provide for electronic design automation (EDA) techniques that check whether individual blocks, such as transistors or other semiconductor devices, are connected to their correct power domains during design. In this way, the disclosed EDA techniques can limit or prevent overstress conditions applied to blocks and help to improve reliability of integrated circuits, when manufactured.
申请公布号 US8510701(B2) 申请公布日期 2013.08.13
申请号 US201213350894 申请日期 2012.01.16
申请人 KO CHEN-TING;CHANG CHIH-HSIEN;PENG YUNG-CHOW;TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. 发明人 KO CHEN-TING;CHANG CHIH-HSIEN;PENG YUNG-CHOW
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
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