| 摘要 |
<p>This lock-detection circuit is provided with: a CPU (204); switches (220 to 224) that are controlled by control signals (FAN1 to FANn) outputted from the CPU and supply power to motors (210 to 214); gates (240 to 244) that are controlled by the control signals and output inputted motor-state signals (LD1 to LDn) as signals (XLD1 to XLDn); and an element (232) that outputs a signal (LOCK) consisting of the disjunction of the aforementioned output signals (XLD1 to XLDn). If said signal (LOCK) indicates that a lock has occurred, the CPU determines the whether a lock has occurred for each motor by evaluating the level of the signal (LOCK) with just one of the control signals at a high level. This makes it possible to identify the locked motor.</p> |
