发明名称 INSTRUCTION CONTROL CIRCUIT, PROCESSOR AND INSTRUCTION CONTROL METHOD
摘要 PROBLEM TO BE SOLVED: To avoid any data hazard between a preceding instruction and a following instruction without generating any stall, and to efficiently issue the following instruction when there exists any data dependency relationship between the preceding instruction and the following instruction.SOLUTION: In a vector processor in which a data dependency detection part detects data dependency relationship between a preceding instruction and a following instruction to be input from an instruction buffer, and an instruction issue control part controls the issuance of the instruction on the basis of the detection result, when there exists data dependency relationship between the preceding instruction and the following instruction, the instruction issue control part generates a new instruction which becomes equivalent to processing relating to a vector register having data dependency relationship between the preceding instruction and the following instruction among processing to be executed by the preceding instruction, and issues the new instruction between the preceding instruction and the following instruction. Thus, it is possible to avoid data hazard between the preceding instruction and the following instruction without generating any stall which used to be generated in a conventional manner.
申请公布号 JP2013152544(A) 申请公布日期 2013.08.08
申请号 JP20120012250 申请日期 2012.01.24
申请人 FUJITSU SEMICONDUCTOR LTD 发明人 NISHIKAWA KENJI
分类号 G06F9/38;G06F17/16 主分类号 G06F9/38
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