| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory architecture optimized for random matrix process capability.SOLUTION: The memory includes an N-dimension array of bit cells 300 and logic configured to address each bit cell using N-dimension addressing (NDA), where N is at least two and the array of bit cells is addressable by N orthogonal address spaces. Each bit cell of the N-dimension addressable memory includes a bit storage element, N word lines 320, and N bit lines 332, 334. |
