发明名称 EPITAXY TECHNIQUE FOR REDUCING THREADING DISLOCATIONS IN STRESSED SEMICONDUCTOR COMPOUNDS
摘要 <p>A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer. One or more of a set of growth conditions, a thickness of one or both of the layers, and/or a lattice mismatch between the layers can be configured to create a target level of compressive and/or shear stress within a minimum percentage of the interface between the layers.</p>
申请公布号 WO2013116622(A1) 申请公布日期 2013.08.08
申请号 WO2013US24310 申请日期 2013.02.01
申请人 SENSOR ELECTRONIC TECHNOLOGY, INC. 发明人 SUN, WENHONG;JAIN, RAKESH;YANG, JINWEI;SHATALOV, MAXIM S.;DOBRINSKY, ALEXANDER;GASKA, REMIGIJUS;SHUR, MICHAEL
分类号 H01L21/20;H01L33/00 主分类号 H01L21/20
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