| 摘要 |
PROBLEM TO BE SOLVED: To reproduce high sound quality audio by regenerating a high quality clock with jitter suppressed.SOLUTION: In a clock regeneration circuit 104, a frequency detection circuit 101 measures the time in which an input clock CK1 changes a predetermined number of times, and outputs a count value proportional to the time. A division ratio generation circuit 102 truncates bits of the output of the frequency detection circuit 101 by means of a quantizer, and outputs the resultant value as a division ratio. A variable frequency divider 103 divides a master clock at the division ratio output from the division ratio generation circuit 102, and outputs the resultant clock as a new clock CK2. |
