发明名称 TEST CONTROLLER FOR 3D STACKED INTEGRATED CIRCUITS
摘要 <p>Stacked IC devices (or 3D semiconductor devices) have two or more semiconductor devices stacked so they occupy less space than two or more conventionally arranged semiconductor devices. Access to test infrastructures of stacked ICs is provided, regardless of configuration, while using a reduced number of interface pins. A master test controller is provided in a base die and at least one slave test controller is provided in another die. The master test controller is coupled to a test data control (TDC) bus and is configured to broadcast test instructions, test data, and an ID of a slave test controller. The slave test controller is also coupled to the TDC bus, is configured to recognize the broadcast test instructions and test data addressed to the slave test controller, and responds to the instructions when the instructions are addressed to the slave test controller.</p>
申请公布号 WO2013116725(A1) 申请公布日期 2013.08.08
申请号 WO2013US24445 申请日期 2013.02.01
申请人 QUALCOMM INCORPORATED 发明人 BHAWMIK, SUDIPTA
分类号 G01R31/3185 主分类号 G01R31/3185
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