发明名称 |
Method for non-shrinkable IP integration |
摘要 |
A method of designing integrated circuits includes providing a design of an integrated circuit at a first scale, wherein the integrated circuit includes a shrinkable circuit including a first intellectual property (IP); and a non-shrinkable circuit including a second IP having a hierarchical structure. A marker layer is formed to cover the non-shrinkable circuit, wherein the shrinkable circuit is not covered by the marker layer. The electrical performance of the non-shrinkable circuit is simulated using a simulation tool, wherein the simulated non-shrinkable circuit is at a second scale smaller than the first scale.
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申请公布号 |
US8504965(B2) |
申请公布日期 |
2013.08.06 |
申请号 |
US20100895264 |
申请日期 |
2010.09.30 |
申请人 |
LIU HUNG-YI;WANG CHUNG-HSING;HOU YUNG-CHIN;JUANG LIE-SZU;TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
LIU HUNG-YI;WANG CHUNG-HSING;HOU YUNG-CHIN;JUANG LIE-SZU |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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地址 |
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