发明名称 Column command buffer and latency circuit including the same
摘要 A column command buffer includes a variable delay section configured to determine a delay time based on a frequency of a clock, and output a column command after delaying it by the delay time; and a buffering section configured to receive an output of the variable delay section and generate internal column commands.
申请公布号 US8503256(B2) 申请公布日期 2013.08.06
申请号 US20100841095 申请日期 2010.07.21
申请人 KO JAE BUM;SK HYNIX INC. 发明人 KO JAE BUM
分类号 G11C7/00 主分类号 G11C7/00
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