发明名称 Computer system with synchronization/desynchronization controller
摘要 A computer system includes a processor, a submodule connected to the processor, an external access monitor configured to monitor a data transfer between the processor and the submodule, and a synchronization/desynchronization controller configured to synchronize or desynchronize the clock of the processor with respect to the clock of the submodule, depending on the result of the monitoring. Specifically, the processor clock is synchronized to the submodule clock when the frequency of access to the submodule by the processor is high, and the processor clock is desynchronized with respect to the submodule clock when the access frequency is low.
申请公布号 US8504868(B2) 申请公布日期 2013.08.06
申请号 US201113049249 申请日期 2011.03.16
申请人 BOHNO YUTAKA;PANASONIC CORPORATION 发明人 BOHNO YUTAKA
分类号 G06F15/00 主分类号 G06F15/00
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