发明名称 |
Analysis of circuit designs |
摘要 |
In one embodiment, a method is provided for analyzing a circuit design. For each sub-circuit of a plurality of sub-circuits specified in the circuit design, a logic level probability is determined for each output of the sub-circuit. The logic level probability indicates the probability that an output of the sub-circuit will have a first value in response to possible values of inputs to the sub-circuit. Each logic level probability is converted to a switching probability that indicates a probability that a switching event will occur at the respective output of the sub-circuit within a time period. The switching probability is stored in a memory.
|
申请公布号 |
US8504974(B1) |
申请公布日期 |
2013.08.06 |
申请号 |
US201113232176 |
申请日期 |
2011.09.14 |
申请人 |
TRIMBERGER STEPHEN M.;XILINX, INC. |
发明人 |
TRIMBERGER STEPHEN M. |
分类号 |
G06F9/455;G06F11/22;G06F17/50 |
主分类号 |
G06F9/455 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|