发明名称 |
Processing unit decoding packets with deadlines in communications channel |
摘要 |
A method of processing first and second record packets of real-time information includes computing for each packet a deadline interval and ordering processing of the packets according to the respective deadline intervals. A single-chip integrated circuit has a processor circuit and embedded electronic instructions forming an egress packet control establishing an egress scheduling list structure and operations in the processor circuit that extract a packet deadline intervals, place packets in the egress scheduling list according to deadline intervals; and embed a decoder that decodes the packets according to a priority depending to their deadline intervals.
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申请公布号 |
US8503323(B2) |
申请公布日期 |
2013.08.06 |
申请号 |
US201113179103 |
申请日期 |
2011.07.08 |
申请人 |
WELIN ANDREW W.;TEXAS INSTRUMENTS INCORPORATED |
发明人 |
WELIN ANDREW W. |
分类号 |
H04L1/00;G10L11/02;H04J1/16;H04J3/14;H04L12/28;H04L12/56;H04L12/64;H04L29/02;H04L29/06;H04M3/00 |
主分类号 |
H04L1/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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