| 摘要 |
PURPOSE: A pass transistor and an odd number frequency divider with a 50% duty cycle are provided to reduce additional power consumption. CONSTITUTION: A frequency divider(100) divides a frequency of an input clock signal and outputs a clock signal with a duty cycle. A pass transistor(200) outputs a clock signal with a duty cycle which is corrected by receiving the clock signal and the input clock signal which are outputted from the frequency divider. An output clock buffer(300) transfers the clock signal, which is outputted from the pass transistor, to the outside. |
