发明名称 |
METHOD FOR FORMING A VIA CONTACTING SEVERAL LEVELS OF SEMICONDUCTOR LAYERS |
摘要 |
A method for forming a via connecting a first upper level layer to a second lower level layer, both layers being surrounded with an insulating material, the method including the steps of: a) forming an opening to reach an edge of the first layer, the opening laterally continuing beyond said edge; b) forming a layer of a protection material on said edge only; c) deepening said opening by selectively etching the insulating material to reach the second lower level layer; and d) filling the opening with at least one conductive contact material.
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申请公布号 |
US2013196500(A1) |
申请公布日期 |
2013.08.01 |
申请号 |
US201313748126 |
申请日期 |
2013.01.23 |
申请人 |
STMICROELECTRONICS S.A.;ENERGIES ALTERNATIVES COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX;COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIESALTERNATIVES;STMICROELECTRONICS S.A. |
发明人 |
BATUDE PERRINE;MORAND YVES |
分类号 |
H01L21/768 |
主分类号 |
H01L21/768 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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