| 摘要 |
A memory apparatus includes an array of bit cells arranged in rows and columns, multiple pairs of complementary bit lines, multiple power lines, and multiple voltage control circuits. Each column of the array is selectable by a corresponding pair of complementary bit lines. Each power line is coupled to the bit cells in a corresponding column. The voltage control circuits are coupled to respective columns of the array. Each voltage control circuit is configured to set a voltage level of a respective one of the power lines responsive to logic levels of the pair of complementary bit lines corresponding to the respective column. |
