| 发明名称 |
FORMAT CONVERSION FROM VALUE CHANGE DUMP (VCD) TO UNIVERSAL VERIFICATION METHODOLOGY (UVM) |
| 摘要 |
A system and method is disclosed for functional verification and/or simulation of dies in a multi-die 3D ICs. The system and method include converting an I/O trace, embodied as a Value Change Dump, to one or more Universal Verification Methodology objects. This conversion aids in identify and fixing issues contained in die. |
| 申请公布号 |
US2013198706(A1) |
申请公布日期 |
2013.08.01 |
| 申请号 |
US201213362415 |
申请日期 |
2012.01.31 |
| 申请人 |
MEHTA ASHOK;JOHN STANLEY;GOEL SANDEEP KUMAR;TING KAI-YUAN;TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. |
发明人 |
MEHTA ASHOK;JOHN STANLEY;GOEL SANDEEP KUMAR;TING KAI-YUAN |
| 分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
| 代理机构 |
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