发明名称 CONCATENATED EQUALIZER/TRELLIS DECODER ARCHITECTURE FOR HDTV RECEIVER
摘要 PROBLEM TO BE SOLVED: To provide a concatenated equalizer/trellis decoding system for use in processing a High Definition Television signal.SOLUTION: A re-encoded trellis decoder output (6), rather than an equalizer output (19), is used as an input to a feedback filter (8) of a decision feedback equalizer (4). Hard or soft decision trellis decoding may be applied. In order to account for the latency associated with trellis decoding and the presence of twelve interleaved decoders, feedback from the trellis decoder to the equalizer is performed by replicating the trellis decoder and equalizer hardware in a module (1) that can be cascaded in as many stages as needed to achieve the desired balance between complexity and performance. The present system provides an improvement of between 0.6 and 1.9 decibels. Cascading of two modules (1) is usually sufficient to achieve most of the potential performance improvement.
申请公布号 JP2013150350(A) 申请公布日期 2013.08.01
申请号 JP20130078649 申请日期 2013.04.04
申请人 THOMSON LICENSING 发明人 HEO SEO WEON;PARK JEONGSOON;GELFAND SAUL BRIAN;MARKMAN IVONETE
分类号 H04B7/005;H03M13/25;H03M13/41;H04L1/00;H04L25/03;H04N5/00;H04N5/21;H04N5/44 主分类号 H04B7/005
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