ADPLL CIRCUIT AND PHASE OFFSET REDUCING METHOD

摘要

PROBLEM TO BE SOLVED: To provide an ADPLL circuit that reduces a phase offset.SOLUTION: An ADPLL circuit 10 comprises: an error computation circuit 19 for calculating a phase error between a reference clock FR and a feedback clock FD that is an output signal FO fed back from a digitally controlled oscillator 16; a flip-flop 12 for determining whether the feedback clock FD leads or lags the reference clock FR and outputting lead/lag information; and a phase error addition circuit 23 for, if the phase error is zero, outputting pseudo minor phase error data for phase control of the output signal FO based on the lead/lag information as phase error data PERR.