发明名称 OVERLAY MODEL FOR ALIGNING AND EXPOSING SEMICONDUCTOR WAFERS
摘要 A method of calculating an overlay correction model in an apparatus for the fabrication of a wafer comprising a structural pattern on a substrate and having first overlay marks generated in a first layer and second overlay marks in a second layer. Overlay deviations of a subset of overlay marks are measured providing a subset of overlay model parameters. For a plurality of overlay mark positions the overlay residuals are estimated using the subset of overlay model parameters. A set of process correction parameters derived from the overlay residuals is provided for the plurality of overlay mark positions. The subset of overlay marks is selected in dependence of the distance to the position of the exposure field, and the selected overlay marks are weighted based on the distance between the overlay mark position and the exposure field.
申请公布号 WO2013110664(A1) 申请公布日期 2013.08.01
申请号 WO2013EP51249 申请日期 2013.01.23
申请人 QONIAC GMBH 发明人 HABETS, BORIS
分类号 H01L21/68;G03F7/20;G03F9/00 主分类号 H01L21/68
代理机构 代理人
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