| 摘要 |
<p>A three-dimensional arrangement of memory cells (600 figure 6D)), comprising a plurality of macro cells and direct address methods by the application of three separate currents per macro cell. The memory cells can be arranged in a 3D orientation minimizing overhead wiring. The macro cell comprises a first electrical connector 206 coupled to a three terminal device, the first electrical conductor extending along a first axis 216 and a second perpendicular axis 218 ; a second electrical connector 210 coupled to the three terminal device 208; a memory cell 212 coupled to the second electrical connector 210 which is disposed along the second axis 218; and a third electrical connector 214 coupled to the memory cell, the third electrical connector extending along a second axis 218 and a third axis 220 perpendicular to both the second and first axis. The three terminal device, 208, acts as a gate addressable device to access the memory cell. The three terminal device may be a vertical transistor, more preferably a MESFET or vertical MESFET having a surrounded gate made of a noble metal and a doped polysilicon channel (figures 7A-C). The memory cell is preferably a Phase Change Memory cell (PCM) or a Tunnel Magneto-Resistive Memory cell (TMR).</p> |
