发明名称 Multi-stage pipeline for cache access
摘要 Embodiments of the present disclosure provide a command processing pipeline operatively coupled to an N-way cache and configured to process a sequence of cache commands. A way of the N ways of the cache with which an address of a cache command matches is a hit way for the cache command in case the cache command is a hit. In one embodiment, the command processing pipeline may be configured to receive a first cache command from one of the plurality of processing cores, select a way, from the N ways, as a potential eviction way, and generate, based at least in part on the received first cache command, N selection signals corresponding to the N ways, wherein each selection signal is indicative of whether the corresponding way is (A). the hit way and/or the eviction way, or (B). neither the hit way nor the eviction way.
申请公布号 US8499123(B1) 申请公布日期 2013.07.30
申请号 US201213357787 申请日期 2012.01.25
申请人 ROHANA TAREK;STOLER GIL;MARVELL ISRAEL (M.I.S.L) LTD. 发明人 ROHANA TAREK;STOLER GIL
分类号 G06F13/00 主分类号 G06F13/00
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