发明名称 Multi-level DRAM cell using CHC technology
摘要 A DRAM memory cell includes: a first finFET structure; and a second finFET structure adjacent to the first finFET structure. The second finFET structure includes: a source follower transistor in a first fin of the second finFET structure; an access transistor in a second fin of the second fin FET structure; a write word line; and a read word line stacked above the write word line. When the read word line is fired high, the source follower transistor enables data to be read from the first finFET structure.
申请公布号 US8497550(B2) 申请公布日期 2013.07.30
申请号 US201113046798 申请日期 2011.03.14
申请人 JUENGLING WERNER;NANYA TECHNOLOGY CORP. 发明人 JUENGLING WERNER
分类号 H01L29/76 主分类号 H01L29/76
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