发明名称 |
Method and apparatus for implementing a parameterizable filter block with an electronic design automation tool |
摘要 |
An electric design automation (EDA) tool for generating a design of a system on a field programmable gate array. (FPGA) includes a graphical user interface to create a block based schematic. The EDA tool includes a library that includes a parameterizable filter block selectable by a designer to include in the block based schematic to represent a component in the design that filters data. The EDA tool includes a design adjustment unit to automatically modify previously programmed and selected components and wires in the block based schematic without input from the designer upon determining a change made to the parameterizable filter block by the designer.
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申请公布号 |
US8499262(B1) |
申请公布日期 |
2013.07.30 |
申请号 |
US20100807959 |
申请日期 |
2010.09.17 |
申请人 |
PERRY STEVEN;ALTERA CORPORATION |
发明人 |
PERRY STEVEN |
分类号 |
G06F17/50;G06F9/455;G06F11/22 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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