| 摘要 |
A burst order control circuit includes a signal transmitting unit transmitting a second address as first and second signals in response to a mode signal and a first address, a signal delay unit delaying a read command, the first signal, and the second signal to generate a delayed read command, a first delayed signal, and a second delayed signal, a signal generating unit configured to generate a burst signal in response to the first address and generate first and second transmission signals in response to the delayed read command and the first and second delayed signals, and an output unit sorting and outputting a plurality of data in response to the burst signal, the first transmission signal, and the second transmission signal.
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