发明名称 |
Test method for screening local bit-line defects in a memory array |
摘要 |
A method of detecting manufacturing defects at a memory array may include utilizing test circuitry to provide a selected voltage as drain bias on a bit-line of the memory array where the memory array is configured to employ a first voltage as the drain bias for a read operation and the selected voltage is higher than the first voltage, and determining whether a leakage current indicative of a manufacturing defect between the bit-line and another component of the memory array is present responsive to providing the selected voltage as the drain bias. A corresponding test device is also provided.
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申请公布号 |
US8498168(B2) |
申请公布日期 |
2013.07.30 |
申请号 |
US201113085942 |
申请日期 |
2011.04.13 |
申请人 |
HUANG YIN CHIN;HUANG CHU PANG;CHANG YI FANG;LIU CHENG CHI;YANG CHANG CHAN;LEE MIN KUANG;MACRONIX INTERNATIONAL CO., LTD. |
发明人 |
HUANG YIN CHIN;HUANG CHU PANG;CHANG YI FANG;LIU CHENG CHI;YANG CHANG CHAN;LEE MIN KUANG |
分类号 |
G11C7/00 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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主权项 |
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