| 摘要 |
A pulse width modulated (PWM) signal is received and, over a time interval of the PWM signal, a first count is incremented when the PWM signal is at a first level, and a second count is incremented when the PWM signal is at a second level. At the end of time interval the first count is compared to the second count and, based on the comparison, a decoded bit is generated. Optionally, incrementing the first count is by enabling a first oscillator that increments a first counter, and incrementing the second count is by enabling a second oscillator that increments a second counter. |
