| 摘要 |
A universal matrix computing device comprises three multiport OR gates, bus, two decoders and matrix of 22AND elements, wherein n is a digit capacity of operands. The device additionally comprises k groups of multiport OR elements by number of additional functionalities, and encipherer, wherein output of ij-th AND element is connected to input of l-th OR element of m-th group, which output is connected to l-th input of the encipherer which output is an output of m-th device function result, wherein l is an integral value of m-th fuction of i and j arguments, when m=1,…, k. |
