| 摘要 |
A device for address resolution comprises flip-flops, adder, address input and address output, wherein the device additionally comprises decoder, encipherer, AND gates. The device address input is connected to input of adder which output is connected to input of the decoder which outputs are connected to corresponding inputs of encipherer which output is a device address output. Output of i-th flip=flop is connected to first input of i-th AND gate, which first input and output are connected respectively to i-th input of decoder and i-th input of adder. |
