ASYMMETRICALLY-ARRANGED MEMORIES HAVING REDUCED CURRENT LEAKAGE AND/OR LATENCY, AND RELATED SYSTEMS AND METHODS

摘要

Asymmetrically-arranged memories having reduced current leakage and/or latency, and related systems and methods are disclosed. In one embodiment, a memory comprises a memory access interface (MAI). The memory further comprises a first memory portion(s) accessible by the memory access interface. The first memory portion(s) has a first latency and a first current leakage. The memory further comprises a second memory portion(s) accessible by the memory access interface. To provide an asymmetrical memory arrangement, the first latency of the first memory portion(s) is increased such that the second memory portion(s) has a second latency greater than or equal to the first latency and a second current leakage greater than the first current leakage. In this manner, the overall current leakage of the memory is reduced while not increasing the overall latency of the memory. The first and second memory portion(s) may each be comprised of one or more memory sub-bank(s) and/or one or more memory bank(s).