发明名称 USE OF LOOP AND ADDRESSING MODE INSTRUCTION SET SEMANTICS TO DIRECT HARDWARE PREFETCHING
摘要 <p>Systems and methods for prefetching cache lines into a cache coupled to a processor. A hardware prefetcher is configured to recognize a memory access instruction as an autoincrement-address (AIA) memory access instruction, infer a stride value from an increment field of the AIA instruction, and prefetch lines into the cache based on the stride value. Additionally or alternatively, the hardware prefetcher is configured to recognize that prefetched cache lines are part of a hardware loop, determine a maximum loop count of the hardware loop, and a remaining loop count as a difference between the maximum loop count and a number of loop iterations that have been completed, select a number of cache lines to prefetch, and truncate an actual number of cache lines to prefetch to be less than or equal to the remaining loop count, when the remaining loop count is less than the selected number of cache lines.</p>
申请公布号 WO2013109651(A1) 申请公布日期 2013.07.25
申请号 WO2013US21777 申请日期 2013.01.16
申请人 QUALCOMM INCORPORATED 发明人 SASSONE, PETER, G.;MAMIDI, SUMAN;ABRAHAM, ELIZABETH;VENKUMAHANTI, SURESH, K.;CODRESCU, LUCIAN
分类号 G06F9/30 主分类号 G06F9/30
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